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 4)D／A输出单元
D／A输出单元负责将已累加／减数据转换为模拟信号输出。D／A输出单元时序同步于控制脉冲。如果扫描控制器硬件资源不多，可以给每一个控制量单独配置一个D／A转换器；否则，可以将这些控制量先缓存起来再通过一个D／A转换器输出以减少硬件成本。
5)触发单元
触发单元接收到扫描使能控制字后控制步进脉冲发生单元使能端有效，步进脉冲发生单元开始工作，进而使得整个扫描控制器运转起来。当触发单元内计数器的计数值与接收到的用于计算扫描时间的计数量相同时表明扫描过程已经完成，这时触发单元控制步进脉冲发生单元使能端失效，步进脉冲发生单元停止工作，扫描过程结束。另外，在扫描开始前触发单元接收控制字产生全局中断信号，通过中断处理单元通知运算单元调用各硬件控制量的初始DAC值。
6)中断处理单元
中断处理单元根据预先设定的中断优先级别决定控制运算单元内各模块的先后顺序。中断处理单元由中断寄存器、中断识别模块、复位处理模块三部分组成。组成框图见图2所示。

中断处理过程如下：首先，四种中断分别缓存入四个中断寄存器。中断寄存器使用FIFO存储单元可以储存多个中断，利用FIFO存储单元内部自身的标志位作为逻辑判断依据可以简化我们的设计。其次，中断识别模块检测各FIFO存储单元的空标志位。如果有任意一个FIFO存储单元的空标志位为O，则说明有中断产生，那么中断识别模块将按中断优先级别排序，并产生一个脉冲通知与zui高中断级别相对应的运算单元内的数据调用模块从RAM中读取下一段控制量的初始值。再次，数据调用模块完成读取任务后返回给复位处理模块一个处理程序完成标志。复位处理模块在收到处理程序完成标志后根据输出中断类别产生读脉冲至空标志位为O且中断优先级别zui高的中断寄存器中。此时，中断寄存器的空标志位有可能发生变化。zui后，中断识别模块再次检测所有的空标志是否都为1，如果不是，中断处理单元继续上述过程直到所有的空标志都为1。中断处理过程结束。
7)步进脉冲发生单元
步进脉冲发生单元内包含多个计数器，计数使能由触发单元控制，计数器的模从地址译码／数据缓存单元读取。每隔一定时间，步进脉冲发生单元产生计数脉冲作为累加／减器的时钟并由运算单元内计数器计数。

4 设计实例
以某型号微波毫米波接收机为例。在此接收机中，系统总线设计为串行总线，需要控制的变量有YIG振荡器频率、YIG滤波器中心频率、平坦度补偿数据和预选器带宽控制电压。选用Altera公司的EplkSOQC208—3芯片作为数字扫描控制器芯片，IDT71V016SA20Y作为RAM存储芯片，AD7538KR、DAC8412作为DAC转换芯片。
经测量，YIG振荡器频率开环控制精度达到5MHz(接收机锁相环的锁频范围可达80MHz)，YIG滤波器中心频率控制精度达到3MHz(YIG滤波器3dB带宽zui小处40MHz)，平坦度补偿值误差小于O．2dB，预选器带宽误差小于带宽2％。数字扫描控制器选用60MHz时钟作为外部时钟，在zui忙碌情况下(四种中断同时到来)，完成四种中断处理总时间小于5μs。
通过仿真和测试数字扫描控制器仅使用了FPGA内约70％的资源，可以为今后的模块扩展留有余地。

5 结束语
对于扫描控制器自身硬件来说，我们可以通过将控制量曲线划分更多段、更加逼近真实曲线，达到提高控制精度的目的；通过选用高档的FPGA芯片并提高系统工作时钟，达到提高控制速度的目的。但在实际使用过程中，我们还必须综合考虑硬件自身的性能(如YIG器件磁滞效应、机械开关切换时间、中频滤波器响应时间等)、软件设计复杂度、要求的性能指标等多组因素对扫描控制精度、速度的影响，合理选择划分段数及工作时钟，zui大限度挖掘出接收机潜能。

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