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仪器级的时钟恢复设备
150Mb/s 到28.6Gb/s 连续可调的时钟恢复，覆盖下一代IO标准，包括PCIe3.0、10GBASE-KR、16xFC、25/28G CEI和100GBASE-LR-4/100GBase-ER-4
从100KHz 到12MHz 精确的可调环路带宽；支持USB3.0、SATA 6G和PCIe3.0中24MHz带宽抖动传递函数(JTF)测试
精确、可调、自检测和显示的PLL 环路带宽、peaking 和抖动传递函数(JTF)- 能够得到标准要求的“黄金锁相环”
可调的峰值、一阶或二阶滚降能力
通过USB 接口同BERTScope 集成在一起；或者单独使用，提供PC 远控软件
DC 耦合的数据通路提供了精确的信号完整性
输出全速率或分频时钟。全速率时钟输出14.3Gb/s，半速率时钟输出从14.3Gb/s 到17.5Gb/s 和28.6Gb/s
内建均衡器能够从带有严重ISI 数据中恢复时钟
数据测量能力
边沿密度测量：确定被测信号的边沿密度
SSC(扩频时钟)波形、dF/dt 的观测
适合测试带有大的频率偏移的SSC 应用
可选的直接抖动频谱分析，通过USB 接口在PC 上提供单独的分析软件
可选的“频谱分析”视图，使用光标测量抖动幅度和频率
用户可设定测量抖动频率限定，进行带限的抖动分析
预设PCI Express Gen2 抖动频率限定
可选的PCIe 2.5 、5和8Gb/s PLL 环路分析(需要抖动分析选件)
CR175A和CR286A提供可选HS(高灵敏度输入)的可以为幅 度小于40mV(单端)、20mV(差分)信号s 提供时钟恢复- 这 个选件没有DC 耦合的数据通路
Main features and advantages
Instrument-level clock recovery equipment
Continuously adjustable clock recovery from 150Mb/s to 28.6gb /s, covering next-generation IO standards including PCIe3.0, 10gbase-kr, 16xFC, 25/28g CEI and 100gbase-lr-4/100gbase-er-4
Accurate adjustable loop bandwidth from 100KHz to 12MHz; Support USB3.0, SATA 6G and PCIe3.0 24MHz bandwidth jitter transfer function (JTF) test
Precise, adjustable, self-detecting and displaying PLL loop bandwidth, peaking and jitter transfer functions (JTF)
Adjustable peak, first - or second-order roll - down capability
Integrated with BERTScope via USB interface; Or use alone, provide PC remote control software
Dc-coupled data paths provide precise signal integrity
Output full speed or frequency division clock. Full rate clock output is up to 14.3Gb/s, while half rate clock output ranges from 14.3Gb/s to 17.5Gb/s and 28.6Gb/s
The built-in equalizer can recover the clock from severe ISI data
Data measurement capability
Edge density measurement: to determine the edge density of the measured signal
SSC(spread spectrum clock) waveform, dF/dt observation
Suitable for testing SSC applications with large frequency offset
Optional direct jitter spectrum analysis, through the USB interface on PC to provide a separate analysis software
Optional "spectrum analysis" view, using cursor to measure jitter amplitude and frequency
The user can set the limit of measurement jitter frequency and carry out bａnd limit jitter analysis
Preset PCI Express Gen2 jitter frequency limit
Optional PCIe 2.5, 5 and 8Gb/s PLL loop analysis (jitter analysis option required)
CR175A and CR286A provide optional HS(high sensitivity input), which can provide clock recovery for signals with amplitudes less than 40mV(single terminal) and 20mV(differential) s - this option has no dc-coupled data path
